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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop; positive-edge trigger (3-State)
MB2821
FEATURES
* * * * * * * *
DESCRIPTION
The MB2821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The MB2821 has two 10-bit, edge triggered registers, with each register coupled to ten 3-State output buffers. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before
20-bit positive-edge triggered register Multiple VCC and GND pins minimize switching noise Live insertion/extraction permitted Power-up reset Power-up 3-State Output capability: +64mA/-32mA Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (nOE) controls all ten 3-State buffers independent of the register operation. When nOE is Low, the data in the register appears at the outputs. When nOE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay nCP to nQx Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VO = 0V or VCC; 3-State Outputs disabled; VCC = 5.5V TYPICAL 4.6 4 7 120 UNIT ns pF pF A
ORDERING INFORMATION
PACKAGES 52-pin plastic Quad Flat Pack TEMPERATURE RANGE -40C to +85C ORDER CODE MB2821BB DRAWING NUMBER 1418B
PIN CONFIGURATION
GND 1OE 1CP 1Q3 1Q2 1Q1 1Q0 1D0 1D1 1D2 1D3 Vcc Vcc
LOGIC SYMBOL
52 51 1Q4 1Q5 1Q6 1 2 3 4 5 6 7 8 9
50 49 48 47
46 45 44 43 42
41 40 39 1D4
45
44
42
41
39
38
37
36
35
34
1D0 1D1 1D2 1D3 1D4 1D5 1D6 46 47 1CP 1OE
1D7 1D8
1D9
37 1D6 36 1D7 35 1D8
GND
1Q7 188
1Q9 2Q0 2Q1
MB2821 52-pin PQFP
34 1D9 33 2D0 32 2D1 31 2D2
2Q2 10 2Q3 11 2Q4 12 2Q5 13 14 15 16 2Q6 2Q7 Vcc 17 18 19 20 2Q8 2Q9 2OE GND 21 22 23 24 25 2D9 2D8 2D7 2CP 2D6 26 Vcc
30 GND 29 2D3 28 2D4 27 2D5 21 20
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E E E
1
38 1D5
E E E
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
48 33
49 32
50 31
51 29
1 28
2 27
3 25
5 24
6 23
7 22
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2CP 2OE
2D7 2D8
2D9
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
8
9
10
11
12
13
15
16
18
19
853-1670 10620
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop; positive-edge trigger (3-State)
MB2821
PIN DESCRIPTION
PIN NUMBER 45, 44, 42, 41, 39, 38, 37, 36, 35, 34, 33, 32, 31, 29, 28, 27, 25, 24, 23, 22 48, 49, 50, 51, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18, 19 47, 20 46, 21 4, 17, 30, 43 14, 26, 40, 52 SYMBOL 1D0 - 1D9 2D0 - 2D9 1Q0 - 1Q9 2Q0 - 2Q9 1OE, 2OE 1CP, 2CP GND VCC Data inputs Data outputs Output enable inputs (active-Low) Clock pulse inputs (active rising edge) Ground (0V) Positive supply voltage FUNCTION
LOGIC SYMBOL (IEEE/IEC)
47 46
20 EN C2 21
EN C2
45 44 42 41 39 38 37 36 35 34
2D
1
48 49 50 51 1 2 3 5 6 7
33 32 31 29 28 27 25 24 23 22
2D
1
8 9 10 11 12 13 15 16 18 19
FUNCTION TABLE
INPUTS nOE L L L nCP nDx l h X INTERNAL REGISTER L H NC OUTPUTS nQ0 - nQ9 L H NC Load and read register Hold Disable outputs OPERATING MODE
H= h= L= l= NC= X= Z= = =
H X NC Z H Dn Dn Z High voltage level High voltage level one set-up time prior to the Low-to-High clock transition Low voltage level Low voltage level one set-up time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low to High clock transition Not a Low-to-High clock transition
August 24, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop; positive-edge trigger (3-State)
MB2821
LOGIC DIAGRAM
nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9
D
D
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nCP
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 4.5 0 2.0 0.8 -32 64 5 +85 LIMITS MAX 5.5 VCC V V V V mA mA ns/V C UNIT
August 24, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop; positive-edge trigger (3-State)
MB2821
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C Min VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II IOFF IPU/PD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Low-level output voltage Power-up output voltageNO TAG Input leakage current Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = Don't care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 2.5 3.0 2.0 Typ -0.9 2.9 3.4 2.4 0.42 0.13 0.01 5.0 5.0 5.0 -5.0 5.0 -70 120 54 120 0.5 0.55 0.55 1.0 100 50 50 -50 50 -180 250 76 250 1.5 -50 Max -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 50 50 -50 50 -180 250 76 250 1.5 Tamb = -40C to +85C Min Max -1.2 V V V V V V A A A A A A mA A mA A mA UNIT
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V a transition time of up to 100sec is permitted.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay nCP to nQx Output enable time to High and Low level Output disable time from High and Low level 1 1 3 4 3 4 160 2.5 2.7 1.2 2.2 1.3 1.5 Tamb = +25oC VCC = +5.0V TYP 250 4.4 4.6 3.3 3.8 3.2 3.0 5.6 6.0 4.2 5.1 4.6 4.2 MAX Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 160 2.5 2.7 1.2 2.2 1.3 1.5 6.4 6.7 5.0 5.8 5.0 4.7 MAX MHz ns ns ns UNIT
August 24, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop; positive-edge trigger (3-State)
MB2821
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, High or Low nDx to nCP Hold time, High or Low nDx to nCP nCP pulse width High or Low 2 2 1 1.5 1.0 1.0 1.0 3.5 3.0 Tamb = +25oC VCC = +5.0V TYP 0.6 -0.2 0.3 -0.4 2.2 1.6 MAX Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 1.5 1.0 1.0 1.0 3.5 3.0 MAX ns ns ns UNIT
1/fMAX
nCP
VM
VM
VM
nDx
VM
tw(H) tPHL
tw(L) tPLH VM VM
ts(H)
nQx
CP
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Data Setup and Hold Times
nOE
VM tPZH
VM tPHZ VOH -0.3V 0V
nOE
VM tPZL
nQx
VM
nQx
Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
August 24, 1993
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EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E
VM VM VM th(H) ts(L) th(L) VM VM VM tPLZ VM VOL +0.3V
EEE EEE EEE EEE EEE
AC WAVEFORMS
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop; positive-edge trigger (3-State)
MB2821
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T CL RL VOUT RL
90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90%
tW VM 10%
90%
AMP (V)
0V tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V)
Test Circuit for 3-State Outputs
POSITIVE PULSE 10%
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude MB 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
August 24, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop; positive-edge trigger (3-State)
MB2821
8 7 6 5 ns 4 3 2 1 -55 -35
tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nCP to nQx
6 5 MAX Offset in ns 4 3 2 1 0 -1 -2
Adjustment of tPLH for Load Capacitance and # of Outputs Switching nCP to nQx
20 switching 10 switching 1 switching
4.5VCC 5.5VCC MIN
-15
5
25
45
65
85
105
125
0
50
100
150
200
C tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nCP to nQx
pF Adjustment of tPHL for Load Capacitance and # of Outputs Switching nCP to nQx
20 switching 10 switching 1 switching
8 7
6 5 MAX 4 Offset in ns 3 2 1 0 -1 -2
6 5 ns 4 3 2 1 -55 -35 -15 5 25 45 65 85 105 125 4.5VCC 5.5VCC MIN
0
50
100
150
200
C tPZH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
pF Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOE to nQx
4 3 2 Offset in ns 1 0 MIN -1 -2 20 switching 10 switching 1 switching
6 5 4 ns 3 2 1 0 -55 -35
MAX
4.5VCC 5.5VCC
-15
5
25
45
65
85
105
125
0
50
100
150
200
C
pF
August 24, 1993
7
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop; positive-edge trigger (3-State)
MB2821
7 6 5
tPZL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
5 4 MAX 3 Offset in ns 2 1 0
Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOE to nQx
20 switching 10 switching 1 switching
ns
4 3 2 1 -55 -35 -15 5 25 45 65 85 105
4.5VCC 5.5VCC
MIN -1 -2 125 0 50 100 150 200
C tPHZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
pF Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOE to nQx
6 5 4
10
MAX
8 6 Offset in ns
20 switching 10 switching 1 switching
ns
3 2 1 0 -55 -35 -15 5 25 45 65 85 105
4.5VCC 5.5VCC
4 2 0
MIN -2 -4 125 0 50 100 150 200
C tPLZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
pF Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOE to nQx
6 5 4 ns 3 2
6 5 MAX 4 Offset in ns 3 2 1 0 -1 -2
20 switching 10 switching 1 switching
4.5VCC 5.5VCC MIN
1 0 -55 -35 -15 5 25 45 65 85 105 125
0
50
100
150
200
C
pF
August 24, 1993
8
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 10-bit D-type flip-flop; positive-edge trigger (3-State)
MB2821
4
tTLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching
Adjustment of tTLH for Load Capacitance/# of Outputs
9 7 20 switching 10 switching 1 switching
3 5 ns 2 4.5VCC 5.5VCC Offset in ns 3 1 -1 0 -55 -35 -15 5 25 45 65 85 105 125 -3 0 50 100 150
1
200
C tTHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching
pF Adjustment of tTHL for Load Capacitance and # of Outputs Switching
5 4
4
3 Offset in ns
3 4.5VCC 2 1 0 -1
20 switching 10 switching 1 switching
ns
2
5.5VCC
1
0 -55 -35 -15 5 25 45 65 85 105 125
-2 0 50 100 150 200
C
pF
4.0 3.5 3.0 2.5 Volts 2.0 1.5 1.0 0.5 0 0
VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0 to 3V
6 5 125C 25C -55C Volts 4 3 2 1 0 125C 25C -55C -1 -2 -3
VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0 to 3V
125C 25C -55C
125C 25C -55C
50
100
150
200
0
50
100
150
200
pF
pF
August 24, 1993
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